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147
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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 12 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
DATE
2000
IEEE
94views Hardware» more  DATE 2000»
15 years 12 months ago
Shared Memory Implementations of Synchronous Dataflow Specifications
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...
Praveen K. Murthy, Shuvra S. Bhattacharyya
182
Voted
DEXAW
2000
IEEE
88views Database» more  DEXAW 2000»
15 years 12 months ago
Spatio-Temporal Databases: Contentions, Components and Consolidation
Spatio-temporal databases have been the focus of considerable research activity over a significant period. However, there are as of yet very few prototypes of complete systems, f...
Norman W. Paton, Alvaro A. A. Fernandes, Tony Grif...
ICMCS
2000
IEEE
145views Multimedia» more  ICMCS 2000»
15 years 12 months ago
Talking Heads and Synthetic Speech: An Architecture for Supporting Electronic Commerce
Facial animation has been combined with text-to-speech synthesis to create innovative multimodal interfaces. In this paper, we present an architecture for this multimodal interfac...
Jörn Ostermann, David R. Millen
IPPS
2000
IEEE
15 years 12 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
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