Sciweavers

5189 search results - page 664 / 1038
» Modeling architectural patterns using architectural primitiv...
Sort
View
ISLPED
2004
ACM
122views Hardware» more  ISLPED 2004»
16 years 1 months ago
Microarchitectural techniques for power gating of execution units
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-...
Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan,...
IPPS
1997
IEEE
15 years 11 months ago
A Customizable Simulator for Workstation Networks
We present a customizable simulator called netsim for high-performance point-to-point workstation networks that is accurate enough to be used for application-level performance ana...
Mustafa Uysal, Anurag Acharya, Robert Bennett, Joe...
ISSA
2004
15 years 9 months ago
Security Considerations In A Global Message Service Handler Design
: Web services are generally accepted as the most interoperable application interface today on the Web. In the context of a global electronic marketplace this is an essential facto...
Johannes J. van Eeden
193
Voted
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
15 years 7 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
ICPP
2009
IEEE
16 years 2 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...