5189 search results - page 693 / 1038 » Modeling architectural patterns using architectural primitiv... |
165
click to vote
DAC
1999
ACM
15 years 11 months ago
1999
ACM
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
186
Voted
MICRO
1999
IEEE
15 years 11 months ago
1999
IEEE
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
197
click to vote
DAC
1996
ACM
15 years 11 months ago
1996
ACM
1 In this paper, we propose a hybrid approach for estimating the switching activities of the internal nodes in logic circuits. The new approach combines the advantages of the simul...
290
click to vote
DAC
1994
ACM
15 years 11 months ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
195
Voted
ASYNC
2007
IEEE
15 years 11 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...