Sciweavers

5189 search results - page 696 / 1038
» Modeling architectural patterns using architectural primitiv...
Sort
View
DAC
2011
ACM
14 years 7 months ago
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhr...
APCSAC
2006
IEEE
16 years 1 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
16 years 1 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...
PKDD
1998
Springer
273views Data Mining» more  PKDD 1998»
15 years 11 months ago
TextVis: An Integrated Visual Environment for Text Mining
TextVis is a visual data mining system for document collections. Such a collection represents an application domain, and the primary goal of the system is to derive patterns that p...
David Landau, Ronen Feldman, Yonatan Aumann, Moshe...
INFOCOM
2007
IEEE
16 years 1 months ago
Queuing Delays in Randomized Load Balanced Networks
—Valiant’s concept of Randomized Load Balancing (RLB), also promoted under the name ‘two-phase routing’, has previously been shown to provide a cost-effective way of implem...
Ravi Prasad, Peter J. Winzer, Sem C. Borst, Marina...