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» Modelling by supersaturated designs
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173
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ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 12 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
243
Voted
ADHOC
2011
14 years 11 months ago
RadiaLE: A framework for designing and assessing link quality estimators in wireless sensor networks
—Stringent cost and energy constraints impose the use of low-cost and low-power radio transceivers in large-scale wireless sensor networks (WSNs). This fact, together with the ha...
Nouha Baccour, Anis Koubaa, Maissa Ben Jamâa...
178
Voted
DAC
2007
ACM
16 years 8 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
202
Voted
ICRA
2007
IEEE
149views Robotics» more  ICRA 2007»
16 years 1 months ago
daVinci Code: A Multi-Model Simulation and Analysis Tool for Multi-Body Systems
Abstract— This paper discusses the design and current capabilities of a new software tool, dVC, capable of simulating planar systems of bodies experiencing unilateral contacts wi...
Stephen Berard, Jeffrey C. Trinkle, Binh Nguyen, B...
195
Voted
KBSE
2007
IEEE
16 years 1 months ago
Checking threat modeling data flow diagrams for implementation conformance and security
Threat modeling analyzes how an adversary might attack a system by supplying it with malicious data or interacting with it. The analysis uses a Data Flow Diagram (DFD) to describe...
Marwan Abi-Antoun, Daniel Wang, Peter Torr