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DATE
2003
IEEE
117views Hardware» more  DATE 2003»
16 years 28 days ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
EDOC
2003
IEEE
16 years 28 days ago
An Approach to Relate Viewpoints and Modeling Languages
The architectural design of distributed enterprise applications from the viewpoints of different stakeholders has been proposed for some time, for example, as part of RM-ODP and I...
Remco M. Dijkman, Dick A. C. Quartel, Luís ...
TMC
2010
196views more  TMC 2010»
15 years 6 months ago
Joint Routing, Channel Assignment, and Scheduling for Throughput Maximization in General Interference Models
—Throughput optimization in wireless networks with multiple channels and multiple radio interfaces per node is a challenging problem. For general traffic models (given a set of ...
Mahmoud Al-Ayyoub, Himanshu Gupta
DSD
2010
IEEE
221views Hardware» more  DSD 2010»
15 years 5 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
16 years 2 months ago
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
Sawal Ali, Li Ke, Reuben Wilcock, Peter Wilson