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189
Voted
DATE
2009
IEEE
103views Hardware» more  DATE 2009»
16 years 2 months ago
Masking timing errors on speed-paths in logic circuits
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
Mihir R. Choudhury, Kartik Mohanram
193
Voted
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
16 years 2 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...
175
Voted
DATE
2009
IEEE
124views Hardware» more  DATE 2009»
16 years 2 months ago
Design and implementation of scalable, transparent threads for multi-core media processor
—In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the num...
Takeshi Kodaka, Shunsuke Sasaki, Takahiro Tokuyosh...
DATE
2009
IEEE
128views Hardware» more  DATE 2009»
16 years 2 months ago
A case study in distributed deployment of embedded software for camera networks
—We present an embedded software application for the real-time estimation of building occupancy using a network of video cameras. We analyze a series of alternative decomposition...
Francesco Leonardi, Alessandro Pinto, Luca P. Carl...
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
16 years 2 months ago
System-level hardware-based protection of memories against soft-errors
We present a hardware-based approach to improve the resilience of a computer system against the errors occurred in the main memory with the help of error detecting and correcting ...
Valentin Gherman, Samuel Evain, Mickael Cartron, N...