49 search results - page 6 / 10 » Neural Compiler Technology for a Parallel Architecture |
188
Voted
DAC
2003
ACM
16 years 7 months ago
2003
ACM
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system that automatically ma...
170
Voted
SPAA
2006
ACM
16 years 10 days ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
159
Voted
HIPC
1999
Springer
15 years 10 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
195
Voted
IFIP
1998
Springer
15 years 10 months ago
1998
Springer
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel an...
186
Voted
CGO
2010
IEEE
16 years 1 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...