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FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
15 years 11 months ago
Mixing buffers and pass transistors in FPGA routing architectures
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
Mike Sheng, Jonathan Rose
CODES
2000
IEEE
15 years 11 months ago
Compaan: deriving process networks from Matlab for embedded signal processing architectures
This paperpresents the Compaantool that automatically transforms a nestedloopprogram written in Matlab into a processnetwork specification. The processnetworkmodelof computationļ...
Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
IPPS
2000
IEEE
15 years 11 months ago
A Novel Superscalar Architecture for Fast DCT Implementation
This paper presents a new superscalar architecture for fast discrete cosine transform (DCT). Comparing with the general SIMD architecture, it speeds up the DCT computation by a fac...
Zhang Yong, Min Zhang
HPCN
1998
Springer
15 years 11 months ago
Dynamically Trace Scheduled VLIW Architectures
This paper presents a new architecture organisation, the dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code of current RISC o...
Alberto Ferreira de Souza, Peter Rounce
ISCAS
2006
IEEE
120views Hardware» more  ISCAS 2006»
16 years 1 months ago
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation ...
Alexey Lopich, Piotr Dudek