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ISCAS
2005
IEEE
136views Hardware» more  ISCAS 2005»
16 years 24 days ago
Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders
— Low-Density Parity-Check Convolutional Codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes an...
Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
15 years 11 months ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
SAFECOMP
1998
Springer
15 years 11 months ago
Increasing System Safety for By-Wire Applications in Vehicles by Using a Time Triggered Architecture
By-wire systems have been established for several years in the area of aircraft construction and there are now approaches to utilize this technology in vehicles. The required elect...
Thomas Ringler, J. Steiner, R. Belschner, Bernd He...
ETS
2006
IEEE
89views Hardware» more  ETS 2006»
15 years 11 months ago
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
This paper presents a new on-chip time measurement architecture which is based on the Timeto-Digital Conversion (TDC) method that is capable of achieving a timing resolution of te...
Matthew Collins, Bashir M. Al-Hashimi
FPGA
2008
ACM
173views FPGA» more  FPGA 2008»
15 years 8 months ago
The amorphous FPGA architecture
This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance...
Mingjie Lin