We present novel algorithms for efficient hierarchical collision detection and propose a hardware architecture for a single-chip accelerator. We use a hierarchy of bounding volum...
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
Abstract— This paper presents a new oversampling architecture for implementing phase-tracking loop that is commonly utilized for position sensors such that synchro, resolver, and...
In this paper, we propose an alternative QoS architecture for the IEEE 802.16 Standard, that incorporates a priority based packet scheduling and a new traffic shaping. For this, w...
In this paper, we present the implementation of a Magnetic Resonance Imaging (MRI) simulator on a GRID computing architecture. The simulation process is based on the resolution of...
Hugues Benoit-Cattin, F. Bellet, Johan Montagnat, ...