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WSCG
2003
177views more  WSCG 2003»
15 years 8 months ago
An Architecture for Hierarchical Collision Detection
We present novel algorithms for efficient hierarchical collision detection and propose a hardware architecture for a single-chip accelerator. We use a hierarchy of bounding volum...
Gabriel Zachmann, Günter Knittel
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
15 years 7 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
16 years 1 months ago
Phase-tracking loop based on delta-sigma oversampling architecture
Abstract— This paper presents a new oversampling architecture for implementing phase-tracking loop that is commonly utilized for position sensors such that synchro, resolver, and...
Yuichiro Orino, Minoru Kuribayashi Kurosawa, Takas...
CONEXT
2006
ACM
16 years 1 months ago
An alternative QoS architecture for the IEEE 802.16 standard
In this paper, we propose an alternative QoS architecture for the IEEE 802.16 Standard, that incorporates a priority based packet scheduling and a new traffic shaping. For this, w...
Luís Felipe M. de Moraes, Paulo Ditarso Mac...
CCGRID
2003
IEEE
16 years 16 days ago
Magnetic Resonance Imaging (Mri) Simulation On A Grid Computing Architecture
In this paper, we present the implementation of a Magnetic Resonance Imaging (MRI) simulator on a GRID computing architecture. The simulation process is based on the resolution of...
Hugues Benoit-Cattin, F. Bellet, Johan Montagnat, ...