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3DIC
2009
IEEE
184views Hardware» more  3DIC 2009»
16 years 2 months ago
Architectural evaluation of 3D stacked RRAM caches
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...
Dean L. Lewis, HsienHsin S. Lee
LCN
2008
IEEE
16 years 1 months ago
IPclip: An architecture to restore Trust-by-Wire in packet-switched networks
—During the last decades, the Internet has steadily developed into a mass medium. The target group radically changed compared to, e.g., the 90s. Because virtually everyone has ac...
Harald Widiger, Stephan Kubisch, Peter Danielis, J...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
16 years 1 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
HICSS
2007
IEEE
119views Biometrics» more  HICSS 2007»
16 years 1 months ago
Towards Ubiquitous Government Services through Adaptations with Context and Views in a Three-Tier Architecture
With the recent advances in mobile technologies and infrastructures, citizens start to demand for not just mobile but also ubiquitous access to e-government services. Further with...
Dickson K. W. Chiu, Dan Hong, S. C. Cheung, Eleann...
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 11 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden