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ISCA
2003
IEEE
212views Hardware» more  ISCA 2003»
16 years 24 days ago
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...
Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi...
SC
2009
ACM
16 years 5 days ago
Comparative study of one-sided factorizations with multiple software packages on multi-core hardware
The emergence and continuing use of multi-core architectures require changes in the existing software and sometimes even a redesign of the established algorithms in order to take ...
Emmanuel Agullo, Bilel Hadri, Hatem Ltaief, Jack D...
188
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EUROPAR
2006
Springer
15 years 11 months ago
Optimization of Dense Matrix Multiplication on IBM Cyclops-64: Challenges and Experiences
Abstract. This paper presents a study of performance optimization of dense matrix multiplication on IBM Cyclops-64(C64) chip architecture. Although much has been published on how t...
Ziang Hu, Juan del Cuvillo, Weirong Zhu, Guang R. ...
225
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DAGSTUHL
2006
15 years 9 months ago
Physical 2D Morphware and Power Reduction Methods for Everyone
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
Jürgen Becker, Michael Hübner, Katarina ...
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
16 years 4 months ago
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhi...