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DSD
2005
IEEE
104views Hardware» more  DSD 2005»
16 years 1 months ago
Design of Transport Triggered Architecture Processors for Wireless Encryption
Transport Triggered Architecture (TTA) offers a costeffective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this pa...
Panu Hämäläinen, Jari Heikkinen, Ma...
ICIP
2005
IEEE
16 years 1 months ago
Adaptive transcoding proxy architecture for video streaming in mobile networks
Wireless video streaming is an area of extensive research due to the error-prone nature of the radio channel with variations in throughput and delay. In mobile networks, handovers...
Matthias Dick, Jens Brandt, Verena Kahmann, Lars C...
IPPS
2005
IEEE
16 years 1 months ago
Data Redistribution and Remote Method Invocation in Parallel Component Architectures
With the increasing availability of high-performance massively parallel computer systems, the prevalence of sophisticated scientific simulation has grown rapidly. The complexity ...
Felipe Bertrand, Randall Bramley, Alan Sussman, Da...
ISCA
2005
IEEE
126views Hardware» more  ISCA 2005»
16 years 1 months ago
A Tree Based Router Search Engine Architecture with Single Port Memories
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Su...
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
16 years 1 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...