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» Noise-tolerant dynamic circuit design
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ISQED
2008
IEEE
98views Hardware» more  ISQED 2008»
16 years 1 months ago
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
We proposed a combined magnetic and circuit level technique to explore the design methodology of SpinTorque Transfer RAM (SPRAM). A dynamic magnetic model of magnetic tunneling ju...
Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimit...
IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
16 years 22 days ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
16 years 10 days ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
CC
2008
Springer
240views System Software» more  CC 2008»
15 years 8 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
CORR
2010
Springer
133views Education» more  CORR 2010»
15 years 6 months ago
Scalable, Time-Responsive, Digital, Energy-Efficient Molecular Circuits using DNA Strand Displacement
We propose a novel theoretical biomolecular design to implement any Boolean circuit using the mechanism of DNA strand displacement. The design is scalable: all species of DNA stra...
Ehsan Chiniforooshan, David Doty, Lila Kari, Shinn...