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ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
16 years 2 hour ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
SIAMCOMP
2010
109views more  SIAMCOMP 2010»
15 years 1 months ago
Analysis of Delays Caused by Local Synchronization
Synchronization is often necessary in parallel computing, but it can create delays whenever the receiving processor is idle, waiting for the information to arrive. This is especia...
Julia Lipman, Quentin F. Stout
HICSS
2010
IEEE
185views Biometrics» more  HICSS 2010»
16 years 1 months ago
Concurrent Architecture for Automated Malware Classification
This paper introduces a new architecture for automating the generalization of program structure and the recognition of common patterns in the area of malware analysis. By using ma...
Timothy Daly, Luanne Burns
KR
2004
Springer
16 years 13 days ago
Planning Graphs and Knowledge Compilation
One of the major advances in classical planning has been the development of Graphplan. Graphplan builds a layered structure called the planning graph, and then searches this struc...
Hector Geffner
ANLP
2000
141views more  ANLP 2000»
15 years 8 months ago
Aggressive Morphology for Robust Lexical Coverage
This paper describes an approach to providing lexical information for natural language processing in unrestricted domains. A system of approximately 1200 morphological rules is us...
William A. Woods