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ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
15 years 11 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
ASWEC
2007
IEEE
15 years 11 months ago
Explicitly Controlling the Fair Service for Busy Web Servers
There is a growing demand for web applications to provide fair service to the highly concurrent requests. In this paper, we present an approach to addressing this requirement. Bas...
Zhanwen Li, David Levy, Shiping Chen, John Zic
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
16 years 2 months ago
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
Sawal Ali, Li Ke, Reuben Wilcock, Peter Wilson
DAC
2003
ACM
16 years 8 months ago
Support vector machines for analog circuit performance representation
The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parame...
Fernando De Bernardinis, Michael I. Jordan, Albert...
DAC
2005
ACM
16 years 8 months ago
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trad
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
Andrey V. Zykov, Elias Mizan, Margarida F. Jacome,...