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202
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HPCA
2000
IEEE
16 years 23 hour ago
Impact of Heterogeneity on DSM Performance
This paper explores area/parallelism tradeo s in the design of distributed shared-memory (DSM) multiprocessors built out of large single-chip computing nodes. In this context, are...
Renato J. O. Figueiredo, José A. B. Fortes
VLSID
2001
IEEE
200views VLSI» more  VLSID 2001»
16 years 8 months ago
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
16 years 2 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
200
Voted
OTM
2009
Springer
16 years 2 months ago
A Component Assignment Framework for Improved Capacity and Assured Performance in Web Portals
Abstract. Web portals hosting large-scale internet applications have become popular due to the variety of services they provide to their users. These portals are developed using co...
Nilabja Roy, Yuan Xue, Aniruddha S. Gokhale, Larry...
AUTOMOTIVEUI
2009
ACM
16 years 2 months ago
Enhanced auditory menu cues improve dual task performance and are preferred with in-vehicle technologies
Auditory display research for driving has mainly focused on collision warning signals, and recent studies on auditory invehicle information presentation have examined only a limit...
Myounghoon Jeon, Benjamin K. Davison, Michael A. N...