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NOCS
2007
IEEE
16 years 1 months ago
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Thomas William Ainsworth, Timothy Mark Pinkston
RTAS
2007
IEEE
16 years 1 months ago
An Approach for Real-Time Database Modeling and Performance Management
It is challenging to manage the performance of real-time databases (RTDBs) that are often used in data-intensive real-time applications such as agile manufacturing and target trac...
Jisu Oh, Kyoung-Don Kang
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
16 years 16 days ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
MM
2005
ACM
157views Multimedia» more  MM 2005»
16 years 1 months ago
Chameleon: application level power management with performance isolation
In this paper, we present Chameleon—an application-level power management approach for reducing energy consumption in mobile processors. Our approach exports the entire responsi...
Xiaotao Liu, Prashant J. Shenoy, Mark D. Corner
ISCA
2008
IEEE
112views Hardware» more  ISCA 2008»
16 years 2 months ago
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
Onur Mutlu, Thomas Moscibroda