1737 search results - page 188 / 348 » On Interpolation in Existence Logics |
185
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ICSE
2007
IEEE-ACM
16 years 7 months ago
2007
IEEE-ACM
The essence of any modeling approach for product line architectures lies in its ability to express variability. Existing approaches do so by explicitly specifying variation points...
208
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ICCD
2007
IEEE
16 years 4 months ago
2007
IEEE
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
161
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ICCAD
2007
IEEE
16 years 4 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
148
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ICCAD
2005
IEEE
16 years 4 months ago
2005
IEEE
State-equivalence based reduction techniques, e.g. bisimulation minimization, can be used to reduce a state transition system to facilitate subsequent verification tasks. However...
190
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ICCAD
2001
IEEE
16 years 4 months ago
2001
IEEE
Given a test set for stuck-at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don’...