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» On Modeling and Testing of Lithography Related Open Faults i...
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DATE
2008
IEEE
76views Hardware» more  DATE 2008»
16 years 27 days ago
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits
Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu
VTS
1996
IEEE
112views Hardware» more  VTS 1996»
15 years 10 months ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker