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DATE
2010
IEEE
119views Hardware» more  DATE 2010»
16 years 24 days ago
Exploiting local logic structures to optimize multi-core SoC floorplanning
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
16 years 24 days ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...
DATE
2002
IEEE
131views Hardware» more  DATE 2002»
16 years 20 days ago
Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation
As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. For high-spee...
Carlos P. Coelho, Luis Miguel Silveira, Joel R. Ph...
ISORC
2002
IEEE
16 years 18 days ago
Packaging Quality of Service Control Behaviors for Reuse
Two limitations of the current implementations of adaptive QoS behaviors are complexity associated with inserting them into common application contexts and lack of reusability acr...
Richard E. Schantz, Joseph P. Loyall, Michael Atig...
CHI
2010
ACM
16 years 16 days ago
What's your idea?: a case study of a grassroots innovation pipeline within a large software company
Establishing a grassroots innovation pipeline has come to the fore as strategy for nurturing innovation within large organizations. A key element of such pipelines is the use of a...
Brian P. Bailey, Eric Horvitz
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