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» On Random Betweenness Constraints
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207
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ICPP
2002
IEEE
16 years 19 days ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
183
Voted
CDC
2009
IEEE
211views Control Systems» more  CDC 2009»
16 years 13 days ago
On stability of linear switched differential algebraic equations
Abstract— This paper studies linear switched differential algebraic equations (DAEs), i.e., systems defined by a finite family of linear DAE subsystems and a switching signal t...
Daniel Liberzon, Stephan Trenn
228
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LCTRTS
2001
Springer
16 years 4 days ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh
189
Voted
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
16 years 3 days ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
180
Voted
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
16 years 7 hour ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...