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» On the Completeness of Quantum Computation Models
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163
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IPPS
2006
IEEE
16 years 1 months ago
Parallelizing post-placement timing optimization
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
Jiyoun Kim, Marios C. Papaefthymiou, José N...
148
Voted
PAM
2005
Springer
16 years 16 days ago
Revisiting Internet AS-Level Topology Discovery
Abstract. The development of veracious models of the Internet topology has received a lot of attention in the last few years. Many proposed models are based on topologies derived f...
Xenofontas A. Dimitropoulos, Dmitri V. Krioukov, G...
246
Voted
DAC
1997
ACM
15 years 11 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
172
Voted
PRDC
2000
IEEE
15 years 10 months ago
Statistical non-parametric algorithms to estimate the optimal software rejuvenation schedule
In this paper, we extend the classical result by Huang, Kintala, Kolettis and Fulton (1995), and in addition propose a modified stochastic model to determine the software rejuvena...
Tadashi Dohi, Katerina Goseva-Popstojanova, Kishor...
178
Voted
ACL
2010
15 years 5 months ago
Reading between the Lines: Learning to Map High-Level Instructions to Commands
In this paper, we address the task of mapping high-level instructions to sequences of commands in an external environment. Processing these instructions is challenging--they posit...
S. R. K. Branavan, Luke S. Zettlemoyer, Regina Bar...