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» On the Execution of Deep Models
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ASAP
2000
IEEE
142views Hardware» more  ASAP 2000»
15 years 12 months ago
Contention-Conscious Transaction Ordering in Embedded Multiprocessors
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digi...
Mukul Khandelia, Shuvra S. Bhattacharyya
FCCM
2000
IEEE
133views VLSI» more  FCCM 2000»
15 years 12 months ago
Configuration Caching Management Techniques for Reconfigurable Computing
Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of configur...
Zhiyuan Li, Katherine Compton, Scott Hauck
170
Voted
ICCD
2000
IEEE
69views Hardware» more  ICCD 2000»
15 years 12 months ago
Hierarchical Simulation of a Multiprocessor Architecture
When proposing new architectural enhancements, it is also important to account for the hardware complexity. To achieve this goal, we propose to model the new design in a hardware ...
Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 12 months ago
HLS: combining statistical and symbolic simulation to guide microprocessor designs
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
Mark Oskin, Frederic T. Chong, Matthew K. Farrens
212
Voted
WECWIS
2000
IEEE
94views ECommerce» more  WECWIS 2000»
15 years 12 months ago
E-Representative: A Scalability Scheme for E-Commerce
In order to meet the quality of service demanded by a growing number of online customers, e-commerce services need to use scalability techniques. This paper introduces the concept...
Wagner Meira Jr., Daniel A. Menascé, Virgil...