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» On the Meaning of Logical Completeness
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DAC
1996
ACM
15 years 11 months ago
POSE: Power Optimization and Synthesis Environment
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an enviro...
Sasan Iman, Massoud Pedram
ISLPED
1996
ACM
78views Hardware» more  ISLPED 1996»
15 years 11 months ago
Gate-level current waveform simulation of CMOS integrated circuits
We present a new gate-level approach to current simulation. We use a symbolic model of current pulses that takes accurately into account the dependence on the switching conditions...
Alessandro Bogliolo, Luca Benini, Giovanni De Mich...
FPL
1994
Springer
435views Hardware» more  FPL 1994»
15 years 11 months ago
Data-Procedural Languages for FPL-based Machines
This paper introduces a new high level programming language for a novel class of computational devices namely data-procedural machines. These machines are by up to several orders o...
Andreas Ast, Jürgen Becker, Reiner W. Hartens...
PEPM
1993
ACM
15 years 11 months ago
The Correctness of an Optimized Code Generation
For a functional programming language with a lazy standard semantics, we define a strictness analysis by means of abstract interpretation. Using the information from the strictne...
Torben Poort Lange
FSEN
2007
Springer
15 years 11 months ago
Model Checking Temporal Metric Specifications with Trio2Promela
Abstract. We present Trio2Promela, a tool for model checking TRIO specifications by means of Spin. TRIO is a linear-time temporal logic with both future and past operators and a qu...
Domenico Bianculli, Paola Spoletini, Angelo Morzen...