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» On the Meaning of Logical Completeness
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EH
2002
IEEE
112views Hardware» more  EH 2002»
16 years 14 days ago
Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occ...
Adrian Stoica, Ricardo Salem Zebulum, Michael I. F...
ISLPED
2000
ACM
70views Hardware» more  ISLPED 2000»
15 years 12 months ago
An adaptive on-chip voltage regulation technique for low-power applications
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
Nicola Dragone, Akshay Aggarwal, L. Richard Carley
198
Voted
DATE
2004
IEEE
184views Hardware» more  DATE 2004»
15 years 11 months ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
FOSSACS
2008
Springer
15 years 9 months ago
Model Checking Freeze LTL over One-Counter Automata
We study complexity issues related to the model-checking problem for LTL with registers (a.k.a. freeze LTL) over one-counter automata. We consider several classes of one-counter au...
Stéphane Demri, Ranko Lazic, Arnaud Sangnie...
211
Voted
TCAD
2008
124views more  TCAD 2008»
15 years 7 months ago
An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs
Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input corre...
Neil Kettle, Andy King