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FPL
1999
Springer
103views Hardware» more  FPL 1999»
15 years 11 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont
ICNP
1998
IEEE
15 years 11 months ago
Evaluating the Overheads of Source-Directed Quality-of-Service Routing
Quality-of-service (QoS) routing satisfiesapplication performance requirements and optimizes network resource usage but effective path-selection schemes require the distribution o...
Anees Shaikh, Jennifer Rexford, Kang G. Shin
ARITH
1997
IEEE
15 years 11 months ago
Theory and applications for a double-base number system
In this paper we present a rigorous theoretical analysis of the main properties of a double base number system, using bases 2 and 3; in particular we emphasize the sparseness of t...
Vassil S. Dimitrov, Graham A. Jullien, William C. ...
ATS
1997
IEEE
87views Hardware» more  ATS 1997»
15 years 11 months ago
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate in...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
15 years 11 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...