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IPPS
1999
IEEE
15 years 12 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
IPPS
1999
IEEE
15 years 12 months ago
Low-Latency Message Passing on Workstation Clusters using SCRAMNet
Clusters of workstations have emerged as a popular platform for parallel and distributed computing. Commodity high speed networks which are used to connect workstation clusters pr...
Vijay Moorthy, Matthew G. Jacunski, Manoj Pillai, ...
ISCA
1999
IEEE
105views Hardware» more  ISCA 1999»
15 years 12 months ago
The Program Decision Logic Approach to Predicated Execution
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
David I. August, John W. Sias, Jean-Michel Puiatti...
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
15 years 12 months ago
The Block-Based Trace Cache
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
Bryan Black, Bohuslav Rychlik, John Paul Shen
RSP
1999
IEEE
122views Control Systems» more  RSP 1999»
15 years 12 months ago
Incremental Compilation for Logic Emulation
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...
Russell Tessier
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