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» On-chip logic minimization
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TCAD
1998
86views more  TCAD 1998»
15 years 6 months ago
Fast heuristic and exact algorithms for two-level hazard-free logic minimization
None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and auto...
Michael Theobald, Steven M. Nowick
MICAI
2007
Springer
16 years 21 days ago
On Reachability of Minimal Models of Multilattice-Based Logic Programs
In this paper some results are obtained regarding the existence and reachability of minimal fixed points for multiple-valued functions on a multilattice. The concept of inf-preser...
Jesús Medina, Manuel Ojeda-Aciego, Jorge Ru...
ICLP
2007
Springer
16 years 21 days ago
Minimal Logic Programs
aa We consider the problem of obtaining a minimal logic program strongly equivalent (under the stable models semantics) to a given arbitrary propositional theory. We propose a meth...
Pedro Cabalar, David Pearce, Agustín Valver...
ICCAD
1993
IEEE
81views Hardware» more  ICCAD 1993»
15 years 10 months ago
Inverter minimization in multi-level logic networks
In this paper, we look at the problem of inverter minimization in multi-level logic networks. The network is specified in terms of a set of base functions and the inversion opera...
Alok Jain, Randal E. Bryant
ICCAD
1997
IEEE
127views Hardware» more  ICCAD 1997»
15 years 10 months ago
OPTIMIST: state minimization for optimal 2-level logic implementation
We present a novel method for state minimization of incompletely-specified finite state machines. Where classic methods simply minimize the number of states, ours directly addre...
Robert M. Fuhrer, Steven M. Nowick