704 search results - page 81 / 141 » On-chip logic minimization |
201
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IFIP
2004
Springer
16 years 3 days ago
2004
Springer
Abstract We introduce a generic framework for proof carrying code, developed and mechanically verified in Isabelle/HOL. The framework defines and proves sound a verification con...
179
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ISIPTA
2003
IEEE
16 years 1 days ago
2003
IEEE
Dempster’s rule for combining two belief functions assumes the independence of the sources of information. If this assumption is questionable, I suggest to use the least speci...
158
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ISVLSI
2002
IEEE
15 years 11 months ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
180
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
169
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KDD
2009
ACM
16 years 7 months ago
2009
ACM
Correlated or discriminative pattern mining is concerned with finding the highest scoring patterns w.r.t. a correlation measure (such as information gain). By reinterpreting corre...