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ISQED
2010
IEEE
123views Hardware» more  ISQED 2010»
15 years 9 months ago
Yield-constrained digital circuit sizing via sequential geometric programming
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costa...
ASPDAC
2005
ACM
119views Hardware» more  ASPDAC 2005»
15 years 9 months ago
CMP aware shuttle mask floorplanning
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
15 years 9 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
PERCOM
2010
ACM
15 years 9 months ago
Engineering energy-efficient target detection applications in Wireless Sensor Networks
This paper addresses the problem of engineering energy-efficient target detection applications using unattended Wireless Sensor Networks (WSNs) for long-lasting surveillance of are...
Paolo Medagliani, Jeremie Leguay, Vincent Gay, Mar...
ECAI
2008
Springer
15 years 9 months ago
A new Approach for Solving Satisfiability Problems with Qualitative Preferences
The problem of expressing and solving satisfiability problems (SAT) with qualitative preferences is central in many areas of Computer Science and Artificial Intelligence. In previo...
Emanuele Di Rosa, Enrico Giunchiglia, Marco Marate...