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181
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ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
16 years 3 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
197
Voted
IPSN
2009
Springer
16 years 1 months ago
Simultaneous placement and scheduling of sensors
We consider the problem of monitoring spatial phenomena, such as road speeds on a highway, using wireless sensors with limited battery life. A central question is to decide where ...
Andreas Krause, Ram Rajagopal, Anupam Gupta, Carlo...
IPPS
2009
IEEE
16 years 1 months ago
On the complexity of mapping pipelined filtering services on heterogeneous platforms
In this paper, we explore the problem of mapping filtering services on large-scale heterogeneous platforms. Two important optimization criteria should be considered in such a fra...
Anne Benoit, Fanny Dufossé, Yves Robert
HOTI
2008
IEEE
16 years 1 months ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...
207
Voted
CODES
2007
IEEE
16 years 1 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...