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ICCD
2002
IEEE
114views Hardware» more  ICCD 2002»
16 years 4 months ago
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Che...
CDC
2008
IEEE
110views Control Systems» more  CDC 2008»
16 years 1 months ago
Multistage investments with recourse: A single-asset case with transaction costs
— We consider a financial decision problem involving dynamic investment decisions on a single risky instrument over multiple and discrete time periods. Investment returns are as...
Ufuk Topcu, Giuseppe Carlo Calafiore, Laurent El G...
DDECS
2008
IEEE
137views Hardware» more  DDECS 2008»
16 years 1 months ago
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
Zhonghai Lu, Lei Xia, Axel Jantsch
GLOBECOM
2008
IEEE
16 years 1 months ago
Transmitter-Based Minimization of Error Rates in the Downlink of Wireless Systems
—Using CDMA technology, one has to contend with interference in frequency-selective channels caused by multipath propagation and fading. Transmitter-based methods such as Zero Fo...
Fred Richter, Andreas Fischer, René Habendo...
ICCCN
2008
IEEE
16 years 1 months ago
Instrumentation and Analysis of MPI Queue Times on the SeaStar High-Performance Network
—Understanding the communication behavior and network resource usage of parallel applications is critical to achieving high performance and scalability on systems with tens of th...
Ron Brightwell, Kevin T. Pedretti, Kurt B. Ferreir...