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LOPSTR
2000
Springer
15 years 10 months ago
A model for inter-module analysis and optimizing compilation
Francisco Bueno, Maria J. García de la Band...
ICCAD
1995
IEEE
79views Hardware» more  ICCAD 1995»
15 years 10 months ago
Optimal wire sizing and buffer insertion for low power and a generalized delay model
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
ISCAS
1995
IEEE
78views Hardware» more  ISCAS 1995»
15 years 10 months ago
Layout Optimization Using Arbitrarily High Degree Posynomial Models
Piyush K. Sancheti, Sachin S. Sapatnekar