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VLSID
2002
IEEE
123views VLSI» more  VLSID 2002»
16 years 7 months ago
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vija...
183
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VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
16 years 7 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
HPCA
2006
IEEE
16 years 7 months ago
Construction and use of linear regression models for processor performance analysis
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
183
Voted
CHI
2002
ACM
16 years 7 months ago
Acquisition of expanding targets
There exist several user interface widgets that dynamically grow in size in response to the user's focus of attention. Some of these, such as icons in toolbars, expand to fac...
Michael J. McGuffin, Ravin Balakrishnan
335
Voted
POPL
2007
ACM
16 years 7 months ago
Lock allocation
We introduce lock allocation, an automatic technique that takes a multi-threaded program annotated with atomic sections (that must be executed atomically), and infers a lock assig...
Michael Emmi, Jeffrey S. Fischer, Ranjit Jhala, Ru...
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