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ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
16 years 1 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
ITNG
2007
IEEE
16 years 1 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
AIME
2007
Springer
16 years 1 months ago
Predictive Modeling of fMRI Brain States Using Functional Canonical Correlation Analysis
We present a novel method for predictive modeling of human brain states from functional neuroimaging (fMRI) data. Extending the traditional canonical correlation analysis of discre...
Sennay Ghebreab, Arnold W. M. Smeulders, Pieter W....
CC
2007
Springer
126views System Software» more  CC 2007»
16 years 1 months ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan
CCS
2007
ACM
16 years 1 months ago
Provably secure ciphertext policy ABE
In ciphertext policy attribute-based encryption (CP-ABE), every secret key is associated with a set of attributes, and every ciphertext is associated with an access structure on a...
Ling Cheung, Calvin C. Newport
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