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ICCAD
2005
IEEE
131views Hardware» more  ICCAD 2005»
16 years 4 months ago
Code restructuring for improving cache performance of MPSoCs
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
Guilin Chen, Mahmut T. Kandemir
CGO
2005
IEEE
16 years 27 days ago
A Progressive Register Allocator for Irregular Architectures
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
David Koes, Seth Copen Goldstein
SC
2004
ACM
16 years 21 days ago
A High Performance Java Middleware with a Real Application
Previous experiments with high-performance Java were initially disappointing. After several years of optimization, this paper investigates the current suitability of such object-o...
Fabrice Huet, Denis Caromel, Henri E. Bal
CDC
2009
IEEE
111views Control Systems» more  CDC 2009»
16 years 1 hour ago
On fusion of information from multiple sensors in the presence of analog erasure links
— Consider multiple sensors that transmit data over analog erasure links to an estimation center. The sensors have access to distinct entries of the output vector of a linear and...
Vijay Gupta, Nuno C. Martins
EMO
2006
Springer
158views Optimization» more  EMO 2006»
15 years 11 months ago
The Hypervolume Indicator Revisited: On the Design of Pareto-compliant Indicators Via Weighted Integration
The design of quality measures for approximations of the Pareto-optimal set is of high importance not only for the performance assessment, but also for the construction of multiobj...
Eckart Zitzler, Dimo Brockhoff, Lothar Thiele