868 search results - page 26 / 174 » Optimizing Logic Design Using Boolean Transforms |
162
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
279
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POPL
2008
ACM
16 years 6 months ago
2008
ACM
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
156
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GLVLSI
2006
IEEE
16 years 13 days ago
2006
IEEE
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
169
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FPGA
2004
ACM
15 years 10 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
180
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CHARME
2003
Springer
15 years 11 months ago
2003
Springer
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...