2020 search results - page 270 / 404 » PAPER - Accelerating parallel evaluations of ROCS |
196
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FUZZIEEE
2007
IEEE
15 years 10 months ago
2007
IEEE
Abstract-- This paper presents a comparison of three different design concepts for Genetic Fuzzy systems. We apply a Symbiotic Evolution that uses the Michigan approach and two app...
174
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ICPP
2008
IEEE
16 years 1 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
168
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CLUSTER
2006
IEEE
16 years 29 days ago
2006
IEEE
This paper presents a middleware framework for storing, accessing and analyzing massive-scale semantic graphs. The framework, MSSG, targets scale-free semantic graphs with O(1012 ...
167
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IEEEPACT
2006
IEEE
16 years 28 days ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
219
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ISCA
2006
IEEE
16 years 27 days ago
2006
IEEE
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...