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ISCA
1994
IEEE
123views Hardware» more  ISCA 1994»
15 years 10 months ago
Software-Extended Coherent Shared Memory: Performance and Cost
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
David Chaiken, Anant Agarwal
ACSC
2004
IEEE
15 years 10 months ago
Reducing Register Pressure Through LAER Algorithm
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
Gao Song
FMICS
2006
Springer
15 years 10 months ago
Test Coverage for Loose Timing Annotations
Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...
Claude Helmstetter, Florence Maraninchi, Laurent M...
EDBT
2010
ACM
155views Database» more  EDBT 2010»
15 years 10 months ago
Suffix tree construction algorithms on modern hardware
Suffix trees are indexing structures that enhance the performance of numerous string processing algorithms. In this paper, we propose cache-conscious suffix tree construction algo...
Dimitris Tsirogiannis, Nick Koudas
ACL
2008
15 years 8 months ago
Pivot Approach for Extracting Paraphrase Patterns from Bilingual Corpora
Paraphrase patterns are useful in paraphrase recognition and generation. In this paper, we present a pivot approach for extracting paraphrase patterns from bilingual parallel corp...
Shiqi Zhao, Haifeng Wang, Ting Liu, Sheng Li