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IEEEPACT
2007
IEEE
16 years 1 months ago
A Loop Correlation Technique to Improve Performance Auditing
Performance auditing is an online optimization strategy that empirically measures the effectiveness of an optimization on a particular code region. It has the potential to greatly...
Jeremy Lau, Matthew Arnold, Michael Hind, Brad Cal...
IEEEPACT
2007
IEEE
16 years 1 months ago
Fast Track: Supporting Unsafe Optimizations with Software Speculation
The use of multi-core, multi-processor machines is opening new opportunities for software speculation, where program code is speculatively executed to improve performance at the a...
Kirk Kelsey, Chengliang Zhang, Chen Ding
ISCAS
2007
IEEE
122views Hardware» more  ISCAS 2007»
16 years 1 months ago
Multi-Channel Coherent Detection for Delay-Insensitive Model-Free Adaptive Control
— A mixed-signal architecture for continuous-time multidimensional model-free optimization is presented. It is based on multi-channel coherent modulation and detection that relia...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
ISCAS
2007
IEEE
114views Hardware» more  ISCAS 2007»
16 years 1 months ago
On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs
Abstract— Parallel time-interleaved analog-to-digital converters (TIADCs) are an attractive architecture to realize low-power and high-speed data conversion. As a drawback of suc...
Stefan Mendel, Christian Vogel
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
16 years 1 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...