5553 search results - page 350 / 1111 » Parallel Implementation of Sch |
182
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
180
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CLUSTER
2006
IEEE
16 years 1 months ago
2006
IEEE
MPJ Express is a thread-safe Java messaging library that provides a full implementation
190
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PPOPP
2006
ACM
16 years 1 months ago
2006
ACM
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing the longest-prefix match at 10Gbps speed or higher. IPv6 forwarding further ex...
157
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GLVLSI
1996
IEEE
15 years 11 months ago
1996
IEEE
A VLSI implementation of a programmable router schemefor parallel interconnectionnetwork architectures is presented in this paper. The router executes routing
208
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PVM
1997
Springer
15 years 11 months ago
1997
Springer
We present Ensemble, a message-passing implementation methodology, applied to PVM. Ensemble overcomes problems and complexities in developing applications in messagepassing enviro...