5553 search results - page 479 / 1111 » Parallel Implementation of Sch |
266
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OSDI
2004
ACM
16 years 8 months ago
2004
ACM
MapReduce is a programming model and an associated implementation for processing and generating large data sets. Users specify a map function that processes a key/value pair to ge...
307
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SIGMOD
2008
ACM
16 years 7 months ago
2008
ACM
We present a novel design and implementation of relational join algorithms for new-generation graphics processing units (GPUs). The most recent GPU features include support for wr...
216
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ICS
2009
Tsinghua U.
16 years 2 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
183
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ICPP
2009
IEEE
16 years 2 months ago
2009
IEEE
—The MPI-2 Standard, released in 1997, defined an interface for one-sided communication, also known as remote memory access (RMA). It was designed with the goal that it should p...
203
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ICPP
2009
IEEE
16 years 2 months ago
2009
IEEE
—The implementation and optimization of collective communication operations is an important field of active research. Such operations directly influence application performance...