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SASP
2009
IEEE
170views Hardware» more  SASP 2009»
16 years 2 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
IPPS
2008
IEEE
16 years 2 months ago
Performance characterization and optimization of parallel I/O on the Cray XT
This paper presents an extensive characterization, tuning, and optimization of parallel I/O on the Cray XT supercomputer, named Jaguar, at Oak Ridge National Laboratory. We have c...
Weikuan Yu, Jeffrey S. Vetter, Sarp Oral
ICPP
2006
IEEE
16 years 1 months ago
A Parallel External-Memory Frontier Breadth-First Traversal Algorithm for Clusters of Workstations
— This paper presents a parallel external-memory algorithm for performing a breadth-first traversal of an implicit graph on a cluster of workstations. The algorithm is a paralle...
Robert Niewiadomski, José Nelson Amaral, Ro...
PADS
2006
ACM
16 years 1 months ago
Aurora: An Approach to High Throughput Parallel Simulation
A master/worker paradigm for executing large-scale parallel discrete event simulation programs over networkenabled computational resources is proposed and evaluated. In contrast t...
Alfred Park, Richard M. Fujimoto
IPPS
2005
IEEE
16 years 1 months ago
Monitoring and Debugging Parallel Software with BCS-MPI on Large-Scale Clusters
Buffered CoScheduled (BCS) MPI is a novel implementation of MPI based on global synchronization of all system activities. BCS-MPI imposes a model where all processes and their com...
Juan Fernández, Fabrizio Petrini, Eitan Fra...