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IPPS
2006
IEEE
16 years 1 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
RTAS
2006
IEEE
16 years 1 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
RTSS
2006
IEEE
16 years 1 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
MIR
2006
ACM
157views Multimedia» more  MIR 2006»
16 years 1 months ago
Generating summaries and visualization for large collections of geo-referenced photographs
We describe a framework for automatically selecting a summary set of photos from a large collection of geo-referenced photographs. Such large collections are inherently difficult ...
Alexander Jaffe, Mor Naaman, Tamir Tassa, Marc Dav...
MM
2006
ACM
197views Multimedia» more  MM 2006»
16 years 1 months ago
Virtual observers in a mobile surveillance system
Conventional wide-area video surveillance systems use a network of fixed cameras positioned close to locations of interest. We describe an alternative and flexible approach to w...
Stewart Greenhill, Svetha Venkatesh