Sciweavers

193 search results - page 27 / 39
» Patching Processor Design Errors
Sort
View
165
Voted
MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
16 years 23 days ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt
297
Voted
ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
14 years 10 months ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...
163
Voted
GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
15 years 10 months ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...
166
Voted
ISPASS
2007
IEEE
16 years 19 days ago
Modeling and Characterizing Power Variability in Multicore Architectures
Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors s...
Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ism...
DAC
1997
ACM
15 years 10 months ago
Toward Formalizing a Validation Methodology Using Simulation Coverage
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
Aarti Gupta, Sharad Malik, Pranav Ashar