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IPPS
2006
IEEE
16 years 1 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
GLOBECOM
2007
IEEE
15 years 9 months ago
Adaptive Radio Resource Allocation in Hierarchical QoS Scheduling for IEEE 802.16 Systems
— Future mobile communication systems such as IEEE 802.16 are expected to deliver a variety of multimedia services with diverse QoS requirements. To guarantee the QoS provision, ...
Hua Wang, Lars Dittmann
DAC
1998
ACM
16 years 8 months ago
WELD - An Environment for Web-based Electronic Design
Increasing size and geographical separation of design data and teams has created a need for a network-based electronic design environment that is scaleable, adaptable, secure, hig...
Francis L. Chan, Mark D. Spiller, A. Richard Newto...
IAT
2006
IEEE
16 years 1 months ago
Collaborative RPD Agents Assisting Decision Making in Active Decision Spaces
One of the challenging issues in a distributed time sensitive information rich environment is how to assist the decision makers to make decisions quickly and effectively. This pap...
Guruprasad Airy, Po-Chun Chen, Xiaocong Fan, John ...
HOTI
2005
IEEE
16 years 1 months ago
A Scalable, Self-Routed, Terabit Capacity, Photonic Interconnection Network
We present SPINet (Scalable Photonic Integrated Network), an optical switching architecture particularly designed for photonic integration. The performance of SPINet-based network...
Assaf Shacham, Benjamin G. Lee, Keren Bergman