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» Performance Modelling of the Computational Hardware: A Stati...
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ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
16 years 1 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman
APCSAC
2007
IEEE
16 years 1 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
208
Voted
EUROPAR
2001
Springer
15 years 12 months ago
A Software Architecture for User Transparent Parallel Image Processing on MIMD Computers
Abstract. This paper describes a software architecture that allows image processing researchers to develop parallel applications in a transparent manner. The architecture’s main ...
Frank J. Seinstra, Dennis Koelma, Jan-Mark Geusebr...
USS
2010
15 years 5 months ago
P4P: Practical Large-Scale Privacy-Preserving Distributed Computation Robust against Malicious Users
In this paper we introduce a framework for privacypreserving distributed computation that is practical for many real-world applications. The framework is called Peers for Privacy ...
Yitao Duan, NetEase Youdao, John Canny, Justin Z. ...
ISCA
2012
IEEE
224views Hardware» more  ISCA 2012»
13 years 10 months ago
A first-order mechanistic model for architectural vulnerability factor
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy...