6709 search results - page 926 / 1342 » Performance Modelling of the Computational Hardware: A Stati... |
205
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DATE
2008
IEEE
16 years 2 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
218
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SBACPAD
2005
IEEE
16 years 1 months ago
2005
IEEE
Executing long-running parallel applications in Opportunistic Grid environments composed of heterogeneous, shared user workstations, is a daunting task. Machines may fail, become ...
216
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DATE
2010
IEEE
16 years 23 days ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
199
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DSD
2006
IEEE
15 years 11 months ago
2006
IEEE
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
175
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ISLPED
2007
ACM
15 years 9 months ago
2007
ACM
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...